Deep Neural Network Training Accelerator Designs in ASIC and FPGA

Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.

Original languageEnglish (US)
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages21-22
Number of pages2
ISBN (Electronic)9781728183312
DOIs
StatePublished - Oct 21 2020
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: Oct 21 2020Oct 24 2020

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
CountryKorea, Republic of
CityYeosu
Period10/21/2010/24/20

Keywords

  • convolutional neural networks
  • energy efficiency
  • hardware accelerator
  • on-device training

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture

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