TY - GEN
T1 - Deep Neural Network Training Accelerator Designs in ASIC and FPGA
AU - Venkataramanaiah, Shreyas K.
AU - Yin, Shihui
AU - Cao, Yu
AU - Seo, Jae Sun
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.
AB - In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.
KW - convolutional neural networks
KW - energy efficiency
KW - hardware accelerator
KW - on-device training
UR - http://www.scopus.com/inward/record.url?scp=85100733311&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85100733311&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9333063
DO - 10.1109/ISOCC50952.2020.9333063
M3 - Conference contribution
AN - SCOPUS:85100733311
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 21
EP - 22
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -