A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS

Samuel Leshner, Krzysztof Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

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Engineering & Materials Science