A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS

Samuel Leshner, Krzysztof Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages210-215
Number of pages6
DOIs
StatePublished - Oct 20 2010
EventIEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece
Duration: Jul 5 2010Jul 7 2010

Publication series

NameProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Other

OtherIEEE Annual Symposium on VLSI, ISVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period7/5/107/7/10

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Leshner, S., Berezowski, K., Yao, X., Chalivendra, G., Patel, S., & Vrudhula, S. (2010). A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS. In Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 (pp. 210-215). [5572773] (Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010). https://doi.org/10.1109/ISVLSI.2010.32