A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS

Samuel Leshner; Krzysztof Berezowski; Xiaoyin Yao; Gayathri Chalivendra; Saurabh Patel; Sarma Vrudhula

doi:10.1109/ISVLSI.2010.32

A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS

Samuel Leshner, Krzysztof Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

Original language	English (US)
Title of host publication	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages	210-215
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2010.32
State	Published - Oct 20 2010
Event	IEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece Duration: Jul 5 2010 → Jul 7 2010

Publication series

Name	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Other

Other	IEEE Annual Symposium on VLSI, ISVLSI 2010
Country/Territory	Greece
City	Lixouri, Kefalonia
Period	7/5/10 → 7/7/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2010.32

Cite this

Leshner, S., Berezowski, K., Yao, X., Chalivendra, G., Patel, S., & Vrudhula, S. (2010). A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS. In Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 (pp. 210-215). Article 5572773 (Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010). https://doi.org/10.1109/ISVLSI.2010.32

A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS. / Leshner, Samuel; Berezowski, Krzysztof; Yao, Xiaoyin et al.
Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. 2010. p. 210-215 5572773 (Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Leshner, S, Berezowski, K, Yao, X, Chalivendra, G, Patel, S & Vrudhula, S 2010, A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS. in Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010., 5572773, Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, pp. 210-215, IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, Greece, 7/5/10. https://doi.org/10.1109/ISVLSI.2010.32

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author = "Samuel Leshner and Krzysztof Berezowski and Xiaoyin Yao and Gayathri Chalivendra and Saurabh Patel and Sarma Vrudhula",

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AB - In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

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A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS

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