A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations

Sarvesh Bhardwaj; Sarma Vrudhula

doi:10.1109/VLSID.2007.11

A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations

Sarvesh Bhardwaj, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intra-die correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Loève Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500× compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.

Original language	English (US)
Title of host publication	Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages	589-594
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2007.11
State	Published - 2007
Event	20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India Duration: Jan 6 2007 → Jan 10 2007

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Other

Other	20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
Country/Territory	India
City	Bangalore
Period	1/6/07 → 1/10/07

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSID.2007.11

Cite this

Bhardwaj, S., & Vrudhula, S. (2007). A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (pp. 589-594). Article 4092106 (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2007.11

A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. / Bhardwaj, Sarvesh; Vrudhula, Sarma.
Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. p. 589-594 4092106 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bhardwaj, S & Vrudhula, S 2007, A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. in Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems., 4092106, Proceedings of the IEEE International Conference on VLSI Design, pp. 589-594, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07, Bangalore, India, 1/6/07. https://doi.org/10.1109/VLSID.2007.11

Bhardwaj S, Vrudhula S. A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. p. 589-594. 4092106. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID.2007.11

Bhardwaj, Sarvesh ; Vrudhula, Sarma. / A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. pp. 589-594 (Proceedings of the IEEE International Conference on VLSI Design).

@inproceedings{3466ff12761c4f09aa9a9de4e98628e8,

title = "A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations",

abstract = "This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intra-die correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Lo{\`e}ve Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500× compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.",

author = "Sarvesh Bhardwaj and Sarma Vrudhula",

year = "2007",

doi = "10.1109/VLSID.2007.11",

language = "English (US)",

isbn = "0769527620",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "589--594",

booktitle = "Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems",

note = "20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 ; Conference date: 06-01-2007 Through 10-01-2007",

}

TY - GEN

T1 - A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations

AU - Bhardwaj, Sarvesh

AU - Vrudhula, Sarma

PY - 2007

Y1 - 2007

N2 - This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intra-die correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Loève Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500× compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.

AB - This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intra-die correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Loève Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500× compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.

UR - http://www.scopus.com/inward/record.url?scp=48349142209&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48349142209&partnerID=8YFLogxK

U2 - 10.1109/VLSID.2007.11

DO - 10.1109/VLSID.2007.11

M3 - Conference contribution

AN - SCOPUS:48349142209

SN - 0769527620

SN - 9780769527628

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 589

EP - 594

BT - Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems

T2 - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07

Y2 - 6 January 2007 through 10 January 2007

ER -

A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this