A defect-based compact modeling approach for the reliability of CMOS devices and integrated circuits

Ivan S. Esqueda, Hugh Barnaby

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


Reliability simulations are critical for lifetime prediction and verification of long-term performance of integrated circuits designed in advanced CMOS technologies. The existing techniques for reliability simulation model aging effects using threshold voltage (Vth) shifts that do not reflect the bias-dependence of stress-induced defects. In this work we present a defect-based modeling approach that captures the dynamic effects of both oxide-trapped charge and interface traps through calculations of surface potential. Such defects are attributed to aging effects and to ionizing-radiation damage in advanced CMOS technologies. The approach provides a connection between physics-based reliability models and integrated circuit simulation. The model is implemented as a Verilog-A sub-circuit module and is compatible with standard EDA tools and MOSFET compact models. The model formulation is verified using two-dimensional TCAD simulations. Demonstrations with digital integrated circuit simulations in SPICE and comparisons with calculations using Vth-based models are also presented.

Original languageEnglish (US)
Pages (from-to)81-86
Number of pages6
JournalSolid-State Electronics
StatePublished - 2014


  • CMOS
  • Interface traps
  • NBTI
  • Oxide-trapped charge
  • Reliability
  • Surface potential

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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