A 90 nm bulk CMOS radiation hardened by design cache memory

Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith Holbert

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache architectural state will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.

Original languageEnglish (US)
Article number5550383
Pages (from-to)2089-2097
Number of pages9
JournalIEEE Transactions on Nuclear Science
Volume57
Issue number4 PART 1
DOIs
StatePublished - Aug 1 2010

Keywords

  • CMOS memory integrated circuits
  • heavy ion beams
  • high-speed integrated circuits
  • radiation hardening

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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