Abstract
Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of big-D/small-A mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal big-D/small-A SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.
Original language | English (US) |
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Article number | 4787054 |
Pages (from-to) | 587-592 |
Number of pages | 6 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 17 |
Issue number | 4 |
DOIs | |
State | Published - Apr 2009 |
Keywords
- Cost model
- Defect screening
- Mixed-signal
- Signature analysis
- System-on-chip (SoC) test
- Wafer sort
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering