Abstract
The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient.
Original language | English (US) |
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Article number | 12 |
Pages (from-to) | 1023-1028 |
Number of pages | 6 |
Journal | IEEE Transactions on Electron Devices |
Volume | 57 |
Issue number | 5 |
DOIs | |
State | Published - May 2010 |
Externally published | Yes |
Keywords
- Adders
- Complimentary metal-oxide-semiconductor (CMOS) digital integrated circuits
- Energy-delay tradeoff
- Magnetic tunnel junction (MTJ) logic
- Spin-transfer torque (STT) devices
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering