Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Lerong Cheng, Yan Lin, Lei He, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

Original languageEnglish (US)
Title of host publicationACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
Pages159-168
Number of pages10
DOIs
StatePublished - 2008
Event16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008 - Monterey, CA, United States
Duration: Feb 24 2008Feb 26 2008

Other

Other16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008
CountryUnited States
CityMonterey, CA
Period2/24/082/26/08

Fingerprint

Field programmable gate arrays (FPGA)
Aging of materials

Keywords

  • FPGA architecture
  • FPGA power model

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Cheng, L., Lin, Y., He, L., & Cao, Y. (2008). Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA (pp. 159-168) https://doi.org/10.1145/1344671.1344696

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. / Cheng, Lerong; Lin, Yan; He, Lei; Cao, Yu.

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2008. p. 159-168.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cheng, L, Lin, Y, He, L & Cao, Y 2008, Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. in ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. pp. 159-168, 16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008, Monterey, CA, United States, 2/24/08. https://doi.org/10.1145/1344671.1344696
Cheng L, Lin Y, He L, Cao Y. Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2008. p. 159-168 https://doi.org/10.1145/1344671.1344696
Cheng, Lerong ; Lin, Yan ; He, Lei ; Cao, Yu. / Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2008. pp. 159-168
@inproceedings{9b17b77527ae48a19b7d25b59c2814af,
title = "Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability",
abstract = "This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.",
keywords = "FPGA architecture, FPGA power model",
author = "Lerong Cheng and Yan Lin and Lei He and Yu Cao",
year = "2008",
doi = "10.1145/1344671.1344696",
language = "English (US)",
isbn = "9781595939340",
pages = "159--168",
booktitle = "ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA",

}

TY - GEN

T1 - Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

AU - Cheng, Lerong

AU - Lin, Yan

AU - He, Lei

AU - Cao, Yu

PY - 2008

Y1 - 2008

N2 - This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

AB - This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

KW - FPGA architecture

KW - FPGA power model

UR - http://www.scopus.com/inward/record.url?scp=70349316106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70349316106&partnerID=8YFLogxK

U2 - 10.1145/1344671.1344696

DO - 10.1145/1344671.1344696

M3 - Conference contribution

AN - SCOPUS:70349316106

SN - 9781595939340

SP - 159

EP - 168

BT - ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

ER -