Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Lerong Cheng, Yan Lin, Lei He, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

Original languageEnglish (US)
Title of host publicationFPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Pages159-168
Number of pages10
DOIs
StatePublished - Dec 1 2008
Event16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008 - Monterey, CA, United States
Duration: Feb 24 2008Feb 26 2008

Publication series

NameACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Conference

Conference16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008
CountryUnited States
CityMonterey, CA
Period2/24/082/26/08

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Keywords

  • FPGA architecture
  • FPGA power model

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Cheng, L., Lin, Y., He, L., & Cao, Y. (2008). Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. In FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 159-168). (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA). https://doi.org/10.1145/1344671.1344696