Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Lerong Cheng; Yan Lin; Lei He; Yu Cao

doi:10.1145/1344671.1344696

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Lerong Cheng, Yan Lin, Lei He, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

Original language	English (US)
Title of host publication	FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Pages	159-168
Number of pages	10
DOIs	https://doi.org/10.1145/1344671.1344696
State	Published - 2008
Event	16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008 - Monterey, CA, United States Duration: Feb 24 2008 → Feb 26 2008

Publication series

Name	ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Conference

Conference	16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008
Country/Territory	United States
City	Monterey, CA
Period	2/24/08 → 2/26/08

Keywords

FPGA architecture
FPGA power model

ASJC Scopus subject areas

General Computer Science

Access to Document

10.1145/1344671.1344696

Cite this

Cheng, L., Lin, Y., He, L., & Cao, Y. (2008). Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. In FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 159-168). (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA). https://doi.org/10.1145/1344671.1344696

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. / Cheng, Lerong; Lin, Yan; He, Lei et al.
FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 2008. p. 159-168 (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cheng, L, Lin, Y, He, L & Cao, Y 2008, Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. in FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, pp. 159-168, 16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008, Monterey, CA, United States, 2/24/08. https://doi.org/10.1145/1344671.1344696

Cheng L, Lin Y, He L, Cao Y. Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. In FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 2008. p. 159-168. (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA). doi: 10.1145/1344671.1344696

@inproceedings{9b17b77527ae48a19b7d25b59c2814af,

title = "Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability",

abstract = "This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.",

keywords = "FPGA architecture, FPGA power model",

author = "Lerong Cheng and Yan Lin and Lei He and Yu Cao",

year = "2008",

doi = "10.1145/1344671.1344696",

language = "English (US)",

isbn = "9781595939340",

series = "ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA",

pages = "159--168",

booktitle = "FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays",

note = "16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008 ; Conference date: 24-02-2008 Through 26-02-2008",

}

TY - GEN

T1 - Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

AU - Cheng, Lerong

AU - Lin, Yan

AU - He, Lei

AU - Cao, Yu

PY - 2008

Y1 - 2008

N2 - This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

AB - This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.

KW - FPGA architecture

KW - FPGA power model

UR - http://www.scopus.com/inward/record.url?scp=70349316106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70349316106&partnerID=8YFLogxK

U2 - 10.1145/1344671.1344696

DO - 10.1145/1344671.1344696

M3 - Conference contribution

AN - SCOPUS:70349316106

SN - 9781595939340

T3 - ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

SP - 159

EP - 168

BT - FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

T2 - 16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008

Y2 - 24 February 2008 through 26 February 2008

ER -

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this