Towards efficient neural networks on-a-chip: Joint hardware-algorithm approaches

Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Machine learning algorithms have made significant advances in many applications. However, their hardware implementation on the state-of-the-art platforms still faces several challenges and are limited by various factors, such as memory volume, memory bandwidth and interconnection overhead. The adoption of the crossbar architecture with emerging memory technology partially solves the problem but induces process variation and other concerns. In this paper, we will present novel solutions to two fundamental issues in crossbar implementation of Artificial Intelligence (AI) algorithms: device variation and insufficient interconnections. These solutions are inspired by the statistical properties of algorithms themselves, especially the redundancy in neural network nodes and connections. By Random Sparse Adaptation and pruning the connections following the Small-World model, we demonstrate robust and efficient performance on representative datasets such as MNIST and CIFAR-10. Moreover, we present Continuous Growth and Pruning algorithm for future learning and adaptation on hardware.

Original languageEnglish (US)
Title of host publicationChina Semiconductor Technology International Conference 2019, CSTIC 2019
EditorsCor Claeys, Ru Huang, Hanming Wu, Qinghuang Lin, Steve Liang, Peilin Song, Zhen Guo, Kafai Lai, Ying Zhang, Xinping Qu, Hsiang-Lan Lung, Wenjian Yu
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538674437
DOIs
StatePublished - Mar 2019
Event2019 China Semiconductor Technology International Conference, CSTIC 2019 - Shanghai, China
Duration: Mar 18 2019Mar 19 2019

Publication series

NameChina Semiconductor Technology International Conference 2019, CSTIC 2019

Conference

Conference2019 China Semiconductor Technology International Conference, CSTIC 2019
CountryChina
CityShanghai
Period3/18/193/19/19

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Fingerprint Dive into the research topics of 'Towards efficient neural networks on-a-chip: Joint hardware-algorithm approaches'. Together they form a unique fingerprint.

  • Cite this

    Du, X., Krishnan, G., Mohanty, A., Li, Z., Charan, G., & Cao, Y. (2019). Towards efficient neural networks on-a-chip: Joint hardware-algorithm approaches. In C. Claeys, R. Huang, H. Wu, Q. Lin, S. Liang, P. Song, Z. Guo, K. Lai, Y. Zhang, X. Qu, H-L. Lung, & W. Yu (Eds.), China Semiconductor Technology International Conference 2019, CSTIC 2019 [8755608] (China Semiconductor Technology International Conference 2019, CSTIC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSTIC.2019.8755608