Top contacts for vertical double-gate MOSFETs

J. Moers; St Trellenkamp; M. Goryll; M. Marso; A. Van Der Hart; S. Hogg; S. Mantl; P. Kordoš; H. Lüth

doi:10.1016/S0167-9317(02)00822-5

Top contacts for vertical double-gate MOSFETs

J. Moers, St Trellenkamp, M. Goryll, M. Marso, A. Van Der Hart, S. Hogg, S. Mantl, P. Kordoš, H. Lüth

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

Original language	English (US)
Pages (from-to)	465-471
Number of pages	7
Journal	Microelectronic Engineering
Volume	64
Issue number	1-4
DOIs	https://doi.org/10.1016/S0167-9317(02)00822-5
State	Published - Oct 2002
Externally published	Yes
Event	MAM2002 - Vaals, Netherlands Duration: Mar 3 2002 → Mar 6 2002

Keywords

CMP
Double-gate MOSFET
Nanotechnology
Silicon devices
Vertical MOSFET

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

Access to Document

10.1016/S0167-9317(02)00822-5

Cite this

@article{92d738b41d644a45a48ffe5b78cade27,

title = "Top contacts for vertical double-gate MOSFETs",

abstract = "As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.",

keywords = "CMP, Double-gate MOSFET, Nanotechnology, Silicon devices, Vertical MOSFET",

author = "J. Moers and St Trellenkamp and M. Goryll and M. Marso and {Van Der Hart}, A. and S. Hogg and S. Mantl and P. Kordo{\v s} and H. L{\"u}th",

year = "2002",

month = oct,

doi = "10.1016/S0167-9317(02)00822-5",

language = "English (US)",

volume = "64",

pages = "465--471",

journal = "Microelectronic Engineering",

issn = "0167-9317",

publisher = "Elsevier",

number = "1-4",

note = "MAM2002 ; Conference date: 03-03-2002 Through 06-03-2002",

}

TY - JOUR

T1 - Top contacts for vertical double-gate MOSFETs

AU - Moers, J.

AU - Trellenkamp, St

AU - Goryll, M.

AU - Marso, M.

AU - Van Der Hart, A.

AU - Hogg, S.

AU - Mantl, S.

AU - Kordoš, P.

AU - Lüth, H.

PY - 2002/10

Y1 - 2002/10

N2 - As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

AB - As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

KW - CMP

KW - Double-gate MOSFET

KW - Nanotechnology

KW - Silicon devices

KW - Vertical MOSFET

UR - http://www.scopus.com/inward/record.url?scp=0036776666&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036776666&partnerID=8YFLogxK

U2 - 10.1016/S0167-9317(02)00822-5

DO - 10.1016/S0167-9317(02)00822-5

M3 - Conference article

AN - SCOPUS:0036776666

SN - 0167-9317

VL - 64

SP - 465

EP - 471

JO - Microelectronic Engineering

JF - Microelectronic Engineering

IS - 1-4

T2 - MAM2002

Y2 - 3 March 2002 through 6 March 2002

ER -

Top contacts for vertical double-gate MOSFETs

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this