Top contacts for vertical double-gate MOSFETs

J. Moers, St Trellenkamp, M. Goryll, M. Marso, A. Van Der Hart, S. Hogg, S. Mantl, P. Kordoš, H. Lüth

Research output: Contribution to journalConference article

11 Scopus citations

Abstract

As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

Original languageEnglish (US)
Pages (from-to)465-471
Number of pages7
JournalMicroelectronic Engineering
Volume64
Issue number1-4
DOIs
StatePublished - Oct 1 2002
Externally publishedYes
EventMAM2002 - Vaals, Netherlands
Duration: Mar 3 2002Mar 6 2002

Keywords

  • CMP
  • Double-gate MOSFET
  • Nanotechnology
  • Silicon devices
  • Vertical MOSFET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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  • Cite this

    Moers, J., Trellenkamp, S., Goryll, M., Marso, M., Van Der Hart, A., Hogg, S., Mantl, S., Kordoš, P., & Lüth, H. (2002). Top contacts for vertical double-gate MOSFETs. Microelectronic Engineering, 64(1-4), 465-471. https://doi.org/10.1016/S0167-9317(02)00822-5