TY - GEN
T1 - The BRISC-V platform
T2 - 2019 Workshop on Computer Architecture Education, WCAE 2019
AU - Agrawal, Rashmi
AU - Bandara, Sahan
AU - Ehret, Alan
AU - Isakov, Mihailo
AU - Mark, Miguel
AU - Kinsy, Michel A.
N1 - Publisher Copyright:
© 2019 Association for Computing Machinery.
PY - 2019/6/22
Y1 - 2019/6/22
N2 - Computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.
AB - Computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.
KW - Computer architecture
KW - Computer organization
KW - Generator
KW - Risc-v
KW - Simulator
KW - Verilog
UR - http://www.scopus.com/inward/record.url?scp=85071236381&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85071236381&partnerID=8YFLogxK
U2 - 10.1145/3338698.3338891
DO - 10.1145/3338698.3338891
M3 - Conference contribution
AN - SCOPUS:85071236381
T3 - Proceedings of the Workshop on Computer Architecture Education, WCAE 2019
BT - Proceedings of the Workshop on Computer Architecture Education, WCAE 2019
PB - Association for Computing Machinery, Inc
Y2 - 22 June 2019
ER -