Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Hong Luo; Yu Wang; Yu Cao; Yuan Xie; Yuchun Ma; Huazhong Yang

doi:10.1109/ISVLSI.2012.35

Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

Original language	English (US)
Title of host publication	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages	183-188
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2012.35
State	Published - 2012
Event	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States Duration: Aug 19 2012 → Aug 21 2012

Publication series

Name	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Other

Other	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Country/Territory	United States
City	Amherst, MA
Period	8/19/12 → 8/21/12

Keywords

Mitigation technique
Performance degradation
Random telegraph noise

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2012.35

Cite this

Luo, H., Wang, Y., Cao, Y., Xie, Y., Ma, Y., & Yang, H. (2012). Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. In Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 (pp. 183-188). Article 6296470 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012). https://doi.org/10.1109/ISVLSI.2012.35

Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. / Luo, Hong; Wang, Yu; Cao, Yu et al.
Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 183-188 6296470 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Luo, H, Wang, Y, Cao, Y, Xie, Y, Ma, Y & Yang, H 2012, Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. in Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012., 6296470, Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, pp. 183-188, 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, United States, 8/19/12. https://doi.org/10.1109/ISVLSI.2012.35

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title = "Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits",

abstract = "Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.",

keywords = "Mitigation technique, Performance degradation, Random telegraph noise",

author = "Hong Luo and Yu Wang and Yu Cao and Yuan Xie and Yuchun Ma and Huazhong Yang",

year = "2012",

doi = "10.1109/ISVLSI.2012.35",

language = "English (US)",

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AU - Luo, Hong

AU - Wang, Yu

AU - Cao, Yu

AU - Xie, Yuan

AU - Ma, Yuchun

AU - Yang, Huazhong

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N2 - Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

AB - Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

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ER -

Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Abstract

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Keywords

ASJC Scopus subject areas

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