Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages183-188
Number of pages6
DOIs
StatePublished - 2012
Event2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States
Duration: Aug 19 2012Aug 21 2012

Other

Other2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
CountryUnited States
CityAmherst, MA
Period8/19/128/21/12

Fingerprint

Telegraph
Degradation
Networks (circuits)
Delay circuits
Digital circuits
Tuning

Keywords

  • Mitigation technique
  • Performance degradation
  • Random telegraph noise

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Luo, H., Wang, Y., Cao, Y., Xie, Y., Ma, Y., & Yang, H. (2012). Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. In Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 (pp. 183-188). [6296470] https://doi.org/10.1109/ISVLSI.2012.35

Temporal performance degradation under RTN : Evaluation and mitigation for nanoscale circuits. / Luo, Hong; Wang, Yu; Cao, Yu; Xie, Yuan; Ma, Yuchun; Yang, Huazhong.

Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 183-188 6296470.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Luo, H, Wang, Y, Cao, Y, Xie, Y, Ma, Y & Yang, H 2012, Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. in Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012., 6296470, pp. 183-188, 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, United States, 8/19/12. https://doi.org/10.1109/ISVLSI.2012.35
Luo H, Wang Y, Cao Y, Xie Y, Ma Y, Yang H. Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits. In Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 183-188. 6296470 https://doi.org/10.1109/ISVLSI.2012.35
Luo, Hong ; Wang, Yu ; Cao, Yu ; Xie, Yuan ; Ma, Yuchun ; Yang, Huazhong. / Temporal performance degradation under RTN : Evaluation and mitigation for nanoscale circuits. Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. pp. 183-188
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