Task scheduling of control-data flow graphs for reconfigurable architectures

Arvind Sudarsanam, Dasu Aravind, Sethuraman Panchanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Task scheduling is an essential part of the design cycle of a reconfigurable hardware implementation for a given application. Most of the current multimedia applications provide a large amount of variations to users and hence are control dominated. To arrive at an optimal schedule for such applications would involve a highly complex scheduling algorithm. This paper proposes a low complexity scheduling algorithm that provides a near optimal solution. Existing approaches suggest that Branch and Bound method of scheduling gives the most optimal solution, but at the same time is highly complex. Our approach introduces the concept of an enhanced Partial Critical Path. Our scheduling algorithm generates near-optimal solution at O(n) complexity. Branch and Bound algorithm can be run selectively to approach optimality, thus reducing the overall complexity. Special cases involving loops have also been addressed. The effect of reconfiguration on the schedule has been analyzed and a solution has been proposed.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
EditorsT.P. Plaks
Pages225-231
Number of pages7
StatePublished - 2004
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States
Duration: Jun 21 2004Jun 24 2004

Other

OtherProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
CountryUnited States
CityLas Vegas, NV
Period6/21/046/24/04

Fingerprint

Data flow graphs
Reconfigurable architectures
Scheduling algorithms
Scheduling
Branch and bound method
Reconfigurable hardware

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sudarsanam, A., Aravind, D., & Panchanathan, S. (2004). Task scheduling of control-data flow graphs for reconfigurable architectures. In T. P. Plaks (Ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 (pp. 225-231)

Task scheduling of control-data flow graphs for reconfigurable architectures. / Sudarsanam, Arvind; Aravind, Dasu; Panchanathan, Sethuraman.

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. ed. / T.P. Plaks. 2004. p. 225-231.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sudarsanam, A, Aravind, D & Panchanathan, S 2004, Task scheduling of control-data flow graphs for reconfigurable architectures. in TP Plaks (ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. pp. 225-231, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, Las Vegas, NV, United States, 6/21/04.
Sudarsanam A, Aravind D, Panchanathan S. Task scheduling of control-data flow graphs for reconfigurable architectures. In Plaks TP, editor, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. 2004. p. 225-231
Sudarsanam, Arvind ; Aravind, Dasu ; Panchanathan, Sethuraman. / Task scheduling of control-data flow graphs for reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. editor / T.P. Plaks. 2004. pp. 225-231
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