Synthesis Techniques for CMOS Folded Source-Coupled Logic Circuits

The series-gated, multiplexer-minimization, and variable-entered mapping methods have been applied to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates. A major advantage of FSCL over static logic is that its digital switching noise is about two orders of magnitude smaller. Hence, higher accuracy and speed are achieved in CMOS mixed-signal IC's by the selective use of FSCL in the high-frequency digital subsections. In contrast to conventional static logic, FSCL dissipates dc power. However, its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. However, complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2-μm p-well CMOS process. With V_dd = 5 V, an FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); an FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 3.0 pJ (11.0 pJ).