Synthesis techniques for CMOS folded source-coupled logic circuits

Sailesh R. Maskai, Sayfe Kiaei, David J. Allstot

Research output: Contribution to journalArticle

38 Citations (Scopus)

Abstract

The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propogation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2-μm p-well CMOS process. With Vdd = 5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ).

Original languageEnglish (US)
Pages (from-to)1157-1167
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number8
DOIs
StatePublished - Aug 1992
Externally publishedYes

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Coupled circuits
Logic gates
Logic circuits
Adders
Electric power utilization
Topology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Synthesis techniques for CMOS folded source-coupled logic circuits. / Maskai, Sailesh R.; Kiaei, Sayfe; Allstot, David J.

In: IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, 08.1992, p. 1157-1167.

Research output: Contribution to journalArticle

Maskai, Sailesh R. ; Kiaei, Sayfe ; Allstot, David J. / Synthesis techniques for CMOS folded source-coupled logic circuits. In: IEEE Journal of Solid-State Circuits. 1992 ; Vol. 27, No. 8. pp. 1157-1167.
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