Statistical Timing Analysis using Bounds and Selective Enumeration

Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose the use of a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which could be further reduced using selective enumeration with modest additional run time.

Original languageEnglish (US)
Title of host publicationACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
PublisherAssociation for Computing Machinery (ACM)
Pages29-36
Number of pages8
ISBN (Print)1581135262, 9781581135268
DOIs
StatePublished - 2002
Externally publishedYes
EventACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems - Monterey, CA, United States
Duration: Dec 2 2002Dec 3 2002

Publication series

NameACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Other

OtherACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
CountryUnited States
CityMonterey, CA
Period12/2/0212/3/02

Keywords

  • Algorithms
  • Performance
  • Reliability

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Agarwal, A., Blaauw, D., Zolotov, V., & Vrudhula, S. (2002). Statistical Timing Analysis using Bounds and Selective Enumeration. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (pp. 29-36). (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems). Association for Computing Machinery (ACM). https://doi.org/10.1145/589411.589417