Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on the physical understanding of circuit aging effects, we develop a predictive short term and long term model to characterize NBTI-induced threshold voltage degradation (ΔVth) at transistor level. Due to process variations, we further develop analytical solutions that efficiently predict the statistics of circuit timing under temporal stress and process variations. These solutions prove that circuit aging and its variance can be fully predicted from the characteristics of transistor degradation and circuit performance sensitivity to aged parameters, independent on the type and the amount of process variations. The results are systematically validated by simulation and measurement data from an industrial 65nm technology, enhancing the predictability and efficiency of statistical reliability analysis.