Simulation of single-electron tunneling circuits

We investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures, for potential application in future high density and low power CMOS-nanodevice hybrid circuits. We first review the operation of the single-electron tunneling (SET) transistor to be used in analog processing arrays for image processing applications. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non-linear transfer characteristics for individual cells. The basic SET-CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN-like behavior in attempting to realize different functionality such as shadowing. Finally, we discuss the speed and signal delay in SET networks, and estimate the power consumption of the SET-CNN and compare it to a state-of-the-art CMOS processor.