Abstract

We investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures, for potential application in future high density and low power CMOS-nanodevice hybrid circuits. We first review the operation of the single-electron tunneling (SET) transistor to be used in analog processing arrays for image processing applications. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non-linear transfer characteristics for individual cells. The basic SET-CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN-like behavior in attempting to realize different functionality such as shadowing. Finally, we discuss the speed and signal delay in SET networks, and estimate the power consumption of the SET-CNN and compare it to a state-of-the-art CMOS processor.

Original languageEnglish (US)
Pages (from-to)113-126
Number of pages14
JournalPhysica Status Solidi (B) Basic Research
Volume233
Issue number1
DOIs
StatePublished - Sep 2002

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Nonlinear networks
Electron tunneling
electron tunneling
Networks (circuits)
simulation
CMOS
Array processing
cells
Nanoelectronics
hybrid circuits
Network architecture
Transistors
Image processing
Electric power utilization
image processing
central processing units
Topology
transistors
topology
analogs

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

Cite this

Simulation of single-electron tunneling circuits. / Gerousis, C. P.; Goodnick, Stephen.

In: Physica Status Solidi (B) Basic Research, Vol. 233, No. 1, 09.2002, p. 113-126.

Research output: Contribution to journalArticle

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