Self-timed regenerators for high-speed and low-power on-chip global interconnect

Prashant Singh, Jae Sun Seo, David Blaauw, Dennis Sylvester

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.

Original languageEnglish (US)
Article number4511670
Pages (from-to)673-677
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number6
DOIs
StatePublished - Jun 1 2008
Externally publishedYes

Keywords

  • Circuit
  • Interconnect
  • Repeaters
  • Signaling

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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