Self-Heating in 40 nm SOI MOSFETs on high resistivity, trap-rich substrates

Xiong Zhang, Payam Mehr, Trevor J. Thornton

Research output: Contribution to journalArticle

Abstract

Closely spaced n-channel MOSFETs have been used to compare the self-heating in nominally identical devices fabricated on conventional and high resistivity, trap-rich silicon-on-insulator (SOI) substrates. One of the MOSFETs operates above threshold and in saturation to heat the active silicon, while the other is biased into the sub-threshold regime and operates as a local thermometer. The trap-rich layer in the high resistivity substrates consists of a highly defected, poly-Si layer just below the buried oxide. Grain boundaries in the poly-Si lead to increased phonon scattering compared to single crystal silicon, with a corresponding decrease in thermal conductivity. Despite the reduced thermal conductivity there appears to be no difference in the self-heating between the MOSFETs on the high resistivity, trap-rich substrates compared to those on the conventional low resistivity substrates.

Original languageEnglish (US)
Article number8902209
Pages (from-to)42-46
Number of pages5
JournalIEEE Transactions on Nanotechnology
Volume19
DOIs
StatePublished - Jan 1 2020

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Heating
Silicon
Substrates
Polysilicon
Thermal conductivity
Phonon scattering
Thermometers
Grain boundaries
Single crystals
Oxides
Hot Temperature

Keywords

  • MOSFETs
  • self-heating
  • Silicon-on-insulator (SOI)
  • sub-threshold operation

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Self-Heating in 40 nm SOI MOSFETs on high resistivity, trap-rich substrates. / Zhang, Xiong; Mehr, Payam; Thornton, Trevor J.

In: IEEE Transactions on Nanotechnology, Vol. 19, 8902209, 01.01.2020, p. 42-46.

Research output: Contribution to journalArticle

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