Abstract
This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (1010x reduction in raw FIT rate) for an HBM-like 3D DRAM system. The tier-1 code is a strong symbol-based code that can correct errors due to small granularity faults and detect errors caused by large granularity faults; the tier-2 code is an XOR-based code that corrects errors detected by the tier-1 code. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing reliability and timing performance.
Original language | English (US) |
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Article number | 24 |
Journal | ACM Transactions on Architecture and Code Optimization |
Volume | 13 |
Issue number | 3 |
DOIs | |
State | Published - Sep 2016 |
Keywords
- 3D memory
- Error control coding
- Performance
- Reliability
ASJC Scopus subject areas
- Software
- Information Systems
- Hardware and Architecture