Rapid embedded system testing using verification patterns

Wei Tek Tsai, Lian Yu, Feng Zhu, Raymond Paul

Research output: Contribution to journalArticle

27 Citations (Scopus)

Abstract

A verification pattern approach for rapidly testing real-time embedded systems first classifies system scenarios into patterns. For each scenario pattern, the VP approach then develops a test script template for all the scenarios belonging to that pattern. In this way, instead of developing numerous scripts to test the system, test engineers can customize and reuse a set of script templates to test the entire application, saving significant effort and time.

Original languageEnglish (US)
Pages (from-to)68-75
Number of pages8
JournalIEEE Software
Volume22
Issue number4
DOIs
StatePublished - Jul 2005

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Real time systems
Embedded systems
Computer systems
Engineers
Testing

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Rapid embedded system testing using verification patterns. / Tsai, Wei Tek; Yu, Lian; Zhu, Feng; Paul, Raymond.

In: IEEE Software, Vol. 22, No. 4, 07.2005, p. 68-75.

Research output: Contribution to journalArticle

Tsai, WT, Yu, L, Zhu, F & Paul, R 2005, 'Rapid embedded system testing using verification patterns', IEEE Software, vol. 22, no. 4, pp. 68-75. https://doi.org/10.1109/MS.2005.103
Tsai, Wei Tek ; Yu, Lian ; Zhu, Feng ; Paul, Raymond. / Rapid embedded system testing using verification patterns. In: IEEE Software. 2005 ; Vol. 22, No. 4. pp. 68-75.
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