Random variability modeling and its impact on scaled CMOS circuits

Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V_th) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design.