PVTOL: Providing productivity, performance, and portability to DoD signal processing applications on multicore processors

Hahn Kim, Edward Rutledge, Sharon Sacco, Sanjeev Mohindra, Matthew Marzilli, Jeremy Kepner, Ryan Haney, Jim Daly, Nadya Bliss

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

PVTOL provides an object-oriented C++ API that hides the complexity of multicore architectures within a PGAS programming model, improving programmer productivity. Tasks and conduits enable data flow patterns such as pipelining and round-robining. Hierarchical maps concisely describe how to allocate hierarchical arrays across processor and memory hierarchies and provide a simple API for moving data across these hierarchies. Functors encapsulate computational kernels; new functors can be easily developed using the PVTOL API and can be fused for more efficient computation. Existing computation and communication technologies that are optimized for various architectures are used to achieve high performance. PVTOL abstracts the details of the underlying processor architectures to provide portability. We are actively developing PVTOL for Intel, PowerPC and Cell architectures and intend to add support for more computational kernels on these architectures. FPGAs are becoming popular for accelerating computation in both the high performance computing (HPC) and high performance embedded computing (HPEC) communities. Integrated processor-FPGA technologies are now available from both HPC and HPEC vendors, e.g. Cray and Mercury Computer Systems. We plan to support FPGAs as co-processors in PVTOL. Finally, automated mapping technology has been demonstrated with pMatlab. We plan to begin implementing automated mapping in PVTOL next year. Similar to PVL, as PVTOL matures and is used in more projects at Lincoln, we plan to propose concepts demonstrated in PVTOL to HPEC-SI for adoption into future versions of VSIPL++.

Original languageEnglish (US)
Title of host publication2008 Proceedings of the Department of Defense High Performance Computing Modernization Program
Subtitle of host publicationUsers Group Conference - Solving the Hard Problems
Pages327-333
Number of pages7
DOIs
StatePublished - Dec 1 2008
Event2008 Department of Defense High Performance Computing Modernization Program: Users Group Conference - Solving the Hard Problems - Seattle, WA, United States
Duration: Jul 14 2007Jul 17 2007

Publication series

Name2008 Proceedings of the Department of Defense High Performance Computing Modernization Program: Users Group Conference - Solving the Hard Problems

Other

Other2008 Department of Defense High Performance Computing Modernization Program: Users Group Conference - Solving the Hard Problems
CountryUnited States
CitySeattle, WA
Period7/14/077/17/07

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Theoretical Computer Science

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    Kim, H., Rutledge, E., Sacco, S., Mohindra, S., Marzilli, M., Kepner, J., Haney, R., Daly, J., & Bliss, N. (2008). PVTOL: Providing productivity, performance, and portability to DoD signal processing applications on multicore processors. In 2008 Proceedings of the Department of Defense High Performance Computing Modernization Program: Users Group Conference - Solving the Hard Problems (pp. 327-333). [4755886] (2008 Proceedings of the Department of Defense High Performance Computing Modernization Program: Users Group Conference - Solving the Hard Problems). https://doi.org/10.1109/DoD.HPCMP.UGC.2008.35