Power reduction and power-Delay trade-offs using logic tranformations

Q. I. Wang, Sarma Vrudhula, Gary Yeap, Shantanu Ganguly

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

We present an efficient technique to reduce the switching activity in a technology-mapped CMOS combinational circuit based on local logic transformations. The transformations consist of adding redundant connections or gates so as to reduce switching activity. We describe simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections. Additionally, we give procedures that permit the designer to trade-off power and delay after the transformations. Results of experiments on both the MCNC benchmark circuits and the circuits of a PowerPC microprocessor chip are given. The results indicate that significant power reduction of a CMOS combinational circuit can be achieved with very low area overhead, delay penalty, and computational cost.

Original languageEnglish (US)
Pages (from-to)97-121
Number of pages25
JournalACM Transactions on Design Automation of Electronic Systems
Volume4
Issue number1
StatePublished - 1999

Fingerprint

Combinatorial circuits
Networks (circuits)
Microprocessor chips
Costs
Experiments

Keywords

  • CMOS logic
  • Logic optimization
  • Logic synthesis
  • Low power
  • Power estimation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Power reduction and power-Delay trade-offs using logic tranformations. / Wang, Q. I.; Vrudhula, Sarma; Yeap, Gary; Ganguly, Shantanu.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 1, 1999, p. 97-121.

Research output: Contribution to journalArticle

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