PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.

Original languageEnglish (US)
Title of host publication2021 Symposium on VLSI Technology, VLSI Technology 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487802
StatePublished - 2021
Externally publishedYes
Event41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan
Duration: Jun 13 2021Jun 19 2021

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2021-June
ISSN (Print)0743-1562

Conference

Conference41st Symposium on VLSI Technology, VLSI Technology 2021
Country/TerritoryJapan
CityVirtual, Online
Period6/13/216/19/21

Keywords

  • Custom ISA
  • DNN accelerator
  • In-memory computing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference'. Together they form a unique fingerprint.

Cite this