@inproceedings{91b3d3df940d49b78d900ca5c7915294,
title = "PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference",
abstract = "We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.",
keywords = "Custom ISA, DNN accelerator, In-memory computing",
author = "Shihui Yin and Bo Zhang and Minkyu Kim and Jyotishman Saikia and Soonwan Kwon and Sungmeen Myung and Hyunsoo Kim and Kim, {Sang Joon} and Mingoo Seok and Seo, {Jae Sun}",
note = "Publisher Copyright: {\textcopyright} 2021 JSAP; 41st Symposium on VLSI Technology, VLSI Technology 2021 ; Conference date: 13-06-2021 Through 19-06-2021",
year = "2021",
language = "English (US)",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 Symposium on VLSI Technology, VLSI Technology 2021",
}