Physical design methodologies for soft error mitigation using redundancy

Chandarasekaran Ramamurthy; Srivatsan Chellappa; Lawrence T. Clark

doi:10.1109/RADECS.2015.7365647

Physical design methodologies for soft error mitigation using redundancy

Chandarasekaran Ramamurthy, Srivatsan Chellappa, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.

Original language	English (US)
Title of host publication	2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2015-December
ISBN (Electronic)	9781509002313
DOIs	https://doi.org/10.1109/RADECS.2015.7365647
State	Published - Dec 24 2015
Externally published	Yes
Event	15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 - Moscow, Russian Federation Duration: Sep 14 2015 → Sep 18 2015

Other

Other	15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
Country/Territory	Russian Federation
City	Moscow
Period	9/14/15 → 9/18/15

Keywords

ASIC
Physical Design Methodology
RHBD
Soft-Error mitigation

ASJC Scopus subject areas

Electrical and Electronic Engineering
Radiation

Access to Document

10.1109/RADECS.2015.7365647

Cite this

Physical design methodologies for soft error mitigation using redundancy. / Ramamurthy, Chandarasekaran; Chellappa, Srivatsan; Clark, Lawrence T.
2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December Institute of Electrical and Electronics Engineers Inc., 2015. 7365647.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ramamurthy, C, Chellappa, S & Clark, LT 2015, Physical design methodologies for soft error mitigation using redundancy. in 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. vol. 2015-December, 7365647, Institute of Electrical and Electronics Engineers Inc., 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015, Moscow, Russian Federation, 9/14/15. https://doi.org/10.1109/RADECS.2015.7365647

@inproceedings{ea61fc5146444fb5bf1c5d5065684127,

title = "Physical design methodologies for soft error mitigation using redundancy",

abstract = "This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.",

keywords = "ASIC, Physical Design Methodology, RHBD, Soft-Error mitigation",

author = "Chandarasekaran Ramamurthy and Srivatsan Chellappa and Clark, {Lawrence T.}",

year = "2015",

month = dec,

day = "24",

doi = "10.1109/RADECS.2015.7365647",

language = "English (US)",

volume = "2015-December",

booktitle = "2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 ; Conference date: 14-09-2015 Through 18-09-2015",

}

TY - GEN

T1 - Physical design methodologies for soft error mitigation using redundancy

AU - Ramamurthy, Chandarasekaran

AU - Chellappa, Srivatsan

AU - Clark, Lawrence T.

PY - 2015/12/24

Y1 - 2015/12/24

N2 - This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.

AB - This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.

KW - ASIC

KW - Physical Design Methodology

KW - RHBD

KW - Soft-Error mitigation

UR - http://www.scopus.com/inward/record.url?scp=84973402545&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84973402545&partnerID=8YFLogxK

U2 - 10.1109/RADECS.2015.7365647

DO - 10.1109/RADECS.2015.7365647

M3 - Conference contribution

AN - SCOPUS:84973402545

VL - 2015-December

BT - 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015

Y2 - 14 September 2015 through 18 September 2015

ER -

Physical design methodologies for soft error mitigation using redundancy

Abstract

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this