Physical design methodologies for soft error mitigation using redundancy

Chandarasekaran Ramamurthy, Srivatsan Chellappa, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.

Original languageEnglish (US)
Title of host publication2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-December
ISBN (Electronic)9781509002313
DOIs
StatePublished - Dec 24 2015
Externally publishedYes
Event15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 - Moscow, Russian Federation
Duration: Sep 14 2015Sep 18 2015

Other

Other15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
CountryRussian Federation
CityMoscow
Period9/14/159/18/15

Keywords

  • ASIC
  • Physical Design Methodology
  • RHBD
  • Soft-Error mitigation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation

Fingerprint Dive into the research topics of 'Physical design methodologies for soft error mitigation using redundancy'. Together they form a unique fingerprint.

Cite this