Optimal scheduling of signature analysis for VLSI testing

Yann-Hang Lee, C. M. Krishna

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A simple algorithm that shows how to optimally schedule the test-application and the signature-analysis phases of VLSI testing is presented. The testing process is broken into subintervals, the signature is analyzed at the end of each subinterval, and future tests are aborted if the circuit is found to be faulty, thus saving test time. The mathematical proofs associated with the algorithm are given.

Original languageEnglish (US)
Pages (from-to)336-341
Number of pages6
JournalIEEE Transactions on Computers
Volume40
Issue number3
DOIs
StatePublished - Mar 1991
Externally publishedYes

Fingerprint

Optimal Scheduling
Signature
Scheduling
Testing
Networks (circuits)
Schedule

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Optimal scheduling of signature analysis for VLSI testing. / Lee, Yann-Hang; Krishna, C. M.

In: IEEE Transactions on Computers, Vol. 40, No. 3, 03.1991, p. 336-341.

Research output: Contribution to journalArticle

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