Optimal Scheduling of Signature Analysis for VLSI Testing

Y. H. Lee; C. M. Krishna

doi:10.1109/12.76412

Optimal Scheduling of Signature Analysis for VLSI Testing

Y. H. Lee, C. M. Krishna

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.

Original language	English (US)
Pages (from-to)	336-341
Number of pages	6
Journal	IEEE Transactions on Computers
Volume	40
Issue number	3
DOIs	https://doi.org/10.1109/12.76412
State	Published - Mar 1991
Externally published	Yes

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

Access to Document

10.1109/12.76412

Cite this

@article{1eb4ce61d26e44ebb2797140fd6a8379,

title = "Optimal Scheduling of Signature Analysis for VLSI Testing",

abstract = "Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.",

author = "Lee, {Y. H.} and Krishna, {C. M.}",

year = "1991",

month = mar,

doi = "10.1109/12.76412",

language = "English (US)",

volume = "40",

pages = "336--341",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - Optimal Scheduling of Signature Analysis for VLSI Testing

AU - Lee, Y. H.

AU - Krishna, C. M.

PY - 1991/3

Y1 - 1991/3

N2 - Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.

AB - Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.

UR - http://www.scopus.com/inward/record.url?scp=0026118263&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026118263&partnerID=8YFLogxK

U2 - 10.1109/12.76412

DO - 10.1109/12.76412

M3 - Article

AN - SCOPUS:0026118263

SN - 0018-9340

VL - 40

SP - 336

EP - 341

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 3

ER -

Optimal Scheduling of Signature Analysis for VLSI Testing

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this