Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

Yeow Meng Chee, Charles Colbourn, Alan Chi Hung Ling, Hui Zhang, Xiande Zhang

Research output: Contribution to journalArticle

Abstract

Coupled switched capacitance causes crosstalk in ultra deep submicron/nanometer VLSI fabrication, which leads to power dissipation, delay faults, and logical malfunctions. We present the first memoryless transition bus-encoding technique for power minimization, error-correction, and elimination of crosstalk simultaneously. To accomplish this, we generalize balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. Optimal or asymptotically optimal constant weight codes eliminating each kind of crosstalk are constructed.

Original languageEnglish (US)
Pages (from-to)479-491
Number of pages13
JournalDesigns, Codes, and Cryptography
Volume77
Issue number2-3
DOIs
StatePublished - Dec 3 2015

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Keywords

  • Balanced sampling plan
  • Constant weight codes
  • Crosstalk avoidance
  • Low power code
  • Packing by triples
  • Packing sampling plan avoiding adjacent units

ASJC Scopus subject areas

  • Applied Mathematics
  • Computer Science Applications

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