NoC performance analysis

Umit Y. Ogras; Radu Marculescu

doi:10.1007/978-94-007-3958-1_5

NoC performance analysis

Umit Y. Ogras, Radu Marculescu

Research output: Chapter in Book/Report/Conference proceeding › Chapter

2 Scopus citations

Abstract

Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

Original language	English (US)
Title of host publication	Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures
Publisher	Springer Verlag
Pages	49-74
Number of pages	26
ISBN (Print)	9789400739574
DOIs	https://doi.org/10.1007/978-94-007-3958-1_5
State	Published - 2013

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	184
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

ASJC Scopus subject areas

Industrial and Manufacturing Engineering

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10.1007/978-94-007-3958-1_5

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abstract = "Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.",

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AB - Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

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PB - Springer Verlag

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NoC performance analysis

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