NoC performance analysis

Umit Y. Ogras, Radu Marculescu

Research output: Chapter in Book/Report/Conference proceedingChapter

2 Scopus citations

Abstract

Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

Original languageEnglish (US)
Title of host publicationModeling, Analysis and Optimization of Network-on-Chip Communication Architectures
PublisherSpringer Verlag
Pages49-74
Number of pages26
ISBN (Print)9789400739574
DOIs
StatePublished - 2013
Externally publishedYes

Publication series

NameLecture Notes in Electrical Engineering
Volume184
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering

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