A real-time architecture for the corner-turn transposition algorithm is proposed that uses the inherent parallelism and pipelining of the algorithm. A fundamental cell is defined that represents a matrix element and is capable of handling data B bits in width. The cells are connected in a pipelined fashion along the rows (columns) of the matrix with interconnection between adjacent rows (columns) in a serpentine organization. The architecture is simple in structure and has local interconnection of the elements, which eliminates communication problems and achieves a high throughput as I/O transfers are eliminated. It is easily implementable in VLSI and has a minimum pin-out (2B plus 4 pins). It has a commendable cost/performance ratio and has wide applications in real-time image processing.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - 1987|
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