Multi-level reliability simulation for IC design

Ketul Sutaria, Jyothi Velamala, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.

Original languageEnglish (US)
Title of host publicationICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs
StatePublished - Dec 1 2012
Event2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China
Duration: Oct 29 2012Nov 1 2012

Publication series

NameICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
CountryChina
CityXi'an
Period10/29/1211/1/12

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Electrical and Electronic Engineering

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