Minimizing area and power of sequential CMOS circuits using threshold decomposition

Niranjan Kulkarni; Nishant Nukala; Sarma Vrudhula

Minimizing area and power of sequential CMOS circuits using threshold decomposition

Niranjan Kulkarni, Nishant Nukala, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.

Original language	English (US)
Title of host publication	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages	605-612
Number of pages	8
State	Published - 2012
Event	2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States Duration: Nov 5 2012 → Nov 8 2012

Other

Other	2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012
Country/Territory	United States
City	San Jose, CA
Period	11/5/12 → 11/8/12

Keywords

Boolean Decomposition
Dynamic Power
Leakage Power
Sequential Circuits
Technology Mapping
Threshold Logic
TLL

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications
Software

Cite this

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title = "Minimizing area and power of sequential CMOS circuits using threshold decomposition",

abstract = "This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.",

keywords = "Boolean Decomposition, Dynamic Power, Leakage Power, Sequential Circuits, Technology Mapping, Threshold Logic, TLL",

author = "Niranjan Kulkarni and Nishant Nukala and Sarma Vrudhula",

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language = "English (US)",

pages = "605--612",

booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

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AU - Kulkarni, Niranjan

AU - Nukala, Nishant

AU - Vrudhula, Sarma

PY - 2012

Y1 - 2012

N2 - This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.

AB - This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.

KW - Boolean Decomposition

KW - Dynamic Power

KW - Leakage Power

KW - Sequential Circuits

KW - Technology Mapping

KW - Threshold Logic

KW - TLL

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M3 - Conference contribution

AN - SCOPUS:84872331411

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EP - 612

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

T2 - 2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012

Y2 - 5 November 2012 through 8 November 2012

ER -

Minimizing area and power of sequential CMOS circuits using threshold decomposition

Abstract

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Keywords

ASJC Scopus subject areas

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