Minimizing area and power of sequential CMOS circuits using threshold decomposition

Niranjan Kulkarni, Nishant Nukala, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages605-612
Number of pages8
StatePublished - 2012
Event2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
Duration: Nov 5 2012Nov 8 2012

Other

Other2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012
CountryUnited States
CitySan Jose, CA
Period11/5/1211/8/12

Keywords

  • Boolean Decomposition
  • Dynamic Power
  • Leakage Power
  • Sequential Circuits
  • Technology Mapping
  • Threshold Logic
  • TLL

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

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