TY - GEN
T1 - Memory-aware application mapping on coarse-grained reconfigurable arrays
AU - Kim, Yongjoo
AU - Lee, Jongeun
AU - Shrivastava, Aviral
AU - Yoon, Jonghee
AU - Paek, Yunheung
N1 - Funding Information:
This work was supported by the Korea Science and Engineering Foundation(KOSEF) NRL Program grant funded by the Korea government(MEST) (No. 2009-0083190), the Engineering Research Center of Excellence Program of Korea Ministry of Education, Science and Technology(MEST)/ Korea Science and Engineering Foundation(KOSEF) (R11-2008-007-01001-0), Seoul R&BD Program(10560), the Korea Research Foundation Grant funded by the Korean Government(MOEHRD) (KRF-2007-357-D00225), 2009 Research Fund of the UNIST (Ulsan National Institute of Science and Technology), and grants from Raytheon, Stardust foundation, and NSF (grant no. 0916652).
PY - 2010
Y1 - 2010
N2 - Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Our proposed solution achieves 62% reduction in the energy-delay product, which factors into about 47% and 28% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications, and memory parameters.
AB - Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Our proposed solution achieves 62% reduction in the energy-delay product, which factors into about 47% and 28% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications, and memory parameters.
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U2 - 10.1007/978-3-642-11515-8_14
DO - 10.1007/978-3-642-11515-8_14
M3 - Conference contribution
AN - SCOPUS:77949614384
SN - 3642115144
SN - 9783642115141
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 171
EP - 185
BT - High Performance Embedded Architectures and Compilers - 5th International Conference, HiPEAC 2010, Proceedings
T2 - 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010
Y2 - 25 January 2010 through 27 January 2010
ER -