Abstract
In many applications, such as digital signal processing, data format converters are used to reformat the data transferred between processing modules. In VLSI implementations, these converters consume a large portion of the available resources. Various methods have been proposed to synthesize data format converter architectures while optimizing the number of registers used to store the data. In this paper, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the data format converter. Low power data format converters are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| Editors | Anon |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 460-465 |
| Number of pages | 6 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA Duration: Oct 2 1995 → Oct 4 1995 |
Other
| Other | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
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| City | Austin, TX, USA |
| Period | 10/2/95 → 10/4/95 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering