Iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling

Karam S. Chatha, Ranga Vemuri

Research output: Contribution to journalConference article

29 Scopus citations

Abstract

The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor/intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs.

Original languageEnglish (US)
Pages (from-to)281-293
Number of pages13
JournalDesign Automation for Embedded Systems
Volume5
Issue number3
StatePublished - Aug 1 2000
Event10th IEEE International Workshop on Rapid System Prototyping (RSP'99) - Tampa, FL, USA
Duration: Jun 16 1999Jun 18 1999

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture

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