Abstract
The inverting subset of fan-out-free boolean functions describe the majority of implementable single-output combinatorial static CMOS gates. Given that each function has many expressions, a method for uniquely identifying these functions is presented and used to determine complements. A large and rich standard cell library incorporates many of these functions, but a reduction in cell-height limits their inclusion due to constraints on internal cell routing. This paper presents a method for listing all such functions and rapid analysis of their viability in different cell heights. Finally, the design constraints in advanced technology nodes limit the utility of a large number of these functions. Those limitations and their impact on the resulting reduction in feasible cells are also described.
| Original language | English (US) |
|---|---|
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| DOIs | |
| State | Accepted/In press - Jan 1 2018 |
Fingerprint
Keywords
- Layout
- Libraries
- Logic gates
- Pins
- Routing
- Standards
- Transistors
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells. / Brunhaver, John; Uhrie, Richard; Clark, Lawrence T.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, 01.01.2018.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells
AU - Brunhaver, John
AU - Uhrie, Richard
AU - Clark, Lawrence T.
PY - 2018/1/1
Y1 - 2018/1/1
N2 - The inverting subset of fan-out-free boolean functions describe the majority of implementable single-output combinatorial static CMOS gates. Given that each function has many expressions, a method for uniquely identifying these functions is presented and used to determine complements. A large and rich standard cell library incorporates many of these functions, but a reduction in cell-height limits their inclusion due to constraints on internal cell routing. This paper presents a method for listing all such functions and rapid analysis of their viability in different cell heights. Finally, the design constraints in advanced technology nodes limit the utility of a large number of these functions. Those limitations and their impact on the resulting reduction in feasible cells are also described.
AB - The inverting subset of fan-out-free boolean functions describe the majority of implementable single-output combinatorial static CMOS gates. Given that each function has many expressions, a method for uniquely identifying these functions is presented and used to determine complements. A large and rich standard cell library incorporates many of these functions, but a reduction in cell-height limits their inclusion due to constraints on internal cell routing. This paper presents a method for listing all such functions and rapid analysis of their viability in different cell heights. Finally, the design constraints in advanced technology nodes limit the utility of a large number of these functions. Those limitations and their impact on the resulting reduction in feasible cells are also described.
KW - Layout
KW - Libraries
KW - Logic gates
KW - Pins
KW - Routing
KW - Standards
KW - Transistors
UR - http://www.scopus.com/inward/record.url?scp=85054692883&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85054692883&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2018.2875334
DO - 10.1109/TCSII.2018.2875334
M3 - Article
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
SN - 1549-7747
ER -