TY - JOUR
T1 - Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells
AU - Brunhaver, John
AU - Uhrie, Richard
AU - Clark, Lawrence T.
N1 - Funding Information:
Manuscript received July 31, 2018; accepted September 13, 2018. Date of publication October 10, 2018; date of current version June 26, 2019. This work was supported by Arizona State University. This brief was recommended by Associate Editor D. Chen. (Corresponding author: John Brunhaver.) The authors are with the School of Electrical, Computer, Energy Engineering, Arizona State University, Tempe, AZ 85281 USA (e-mail: john.brunhaver@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - The inverting subset of fan-out-free boolean functions describe the majority of implementable single-output combinatorial static CMOS gates. Given that each function has many expressions, a method for uniquely identifying these functions is presented and used to determine complements. A large and rich standard cell library incorporates many of these functions, but a reduction in cell-height limits their inclusion due to constraints on internal cell routing. This brief presents a method for listing all such functions and rapid analysis of their viability in different cell heights. Finally, the design constraints in advanced technology nodes limit the utility of a large number of these functions. Those limitations and their impact on the resulting reduction in feasible cells are also described.
AB - The inverting subset of fan-out-free boolean functions describe the majority of implementable single-output combinatorial static CMOS gates. Given that each function has many expressions, a method for uniquely identifying these functions is presented and used to determine complements. A large and rich standard cell library incorporates many of these functions, but a reduction in cell-height limits their inclusion due to constraints on internal cell routing. This brief presents a method for listing all such functions and rapid analysis of their viability in different cell heights. Finally, the design constraints in advanced technology nodes limit the utility of a large number of these functions. Those limitations and their impact on the resulting reduction in feasible cells are also described.
KW - Circuits and systems
KW - digital circuits
KW - digital integrated circuits
KW - integrated circuits
KW - very large scale integration circuits and systems
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U2 - 10.1109/TCSII.2018.2875334
DO - 10.1109/TCSII.2018.2875334
M3 - Article
AN - SCOPUS:85054692883
VL - 66
SP - 1164
EP - 1168
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 7
M1 - 8488456
ER -