Intrinsic limitations on device performance and reliability from bond-constraint induced transition regions at interfaces of stacked dielectrics

G. Lucovsky, H. Yang, H. Niimi, J. W. Keister, J. E. Rowe, M. F. Thorpe, J. C. Phillips

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

The performance of MOSFET devices with stacked gate dielectrics was examined. Ultrathin plasma-oxidized Si-SiO2 layers were integrated into devices with SiN, SiON, and Ta2O5 alternative dielectrics. The mechanical bonding strain was studied by combining bond counting on the atomic level with theoretical considerations for network constraints.

Original languageEnglish (US)
Pages (from-to)1742-1748
Number of pages7
JournalJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Volume18
Issue number3
DOIs
StatePublished - May 1 2000

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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