Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection

We propose hardware noise-aware deep neural network (DNN) training to largely improve the DNN inference accuracy of in-memory computing (IMC) hardware. During DNN training, we perform noise injection at the partial sum level, which matches with the crossbar structure of IMC hardware, and the injected noise data is directly based on measurements of actual IMC prototype chips. We evaluated DNNs using measurements from two different SRAM-based IMC prototype designs and five different chips, across different noise characteristics. For various DNNs and IMC chip measurements, our proposed technique consistently improves DNN accuracy for actual IMC hardware.