Highly Digital Second-Order VCO ADC

Akshay Jayaraj, Mohammadhadi Danesh, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

A continuous-time second-order Δ Σ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.

Original languageEnglish (US)
Article number8648369
Pages (from-to)2415-2425
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume66
Issue number7
DOIs
StatePublished - Jul 2019
Externally publishedYes

Keywords

  • analog-to-digital converter
  • continuous-time ΔΣ
  • noise shaping
  • Voltage controlled oscillator (VCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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