TY - JOUR
T1 - Highly Digital Second-Order VCO ADC
AU - Jayaraj, Akshay
AU - Danesh, Mohammadhadi
AU - Chandrasekaran, Sanjeev Tannirkulam
AU - Sanyal, Arindam
N1 - Funding Information:
Manuscript received October 9, 2018; revised January 4, 2019; accepted February 4, 2019. Date of publication February 21, 2019; date of current version June 18, 2019. This work was supported by Semiconductor Research Corporation (SRC) Task 2712.020 through The University of Texas at Dallas’ Texas Analog Center of Excellence (TxACE). This paper was recommended by Associate Editor T.-C. Lee. (Corresponding author: Akshay Jayaraj.) The authors are with the Electrical Engineering Department, University at Buffalo, Buffalo, NY 14260 USA (e-mail: akshayja@buffalo.edu; mdanesh@buffalo.edu; stannirk@buffalo.edu; arindams@buffalo.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - A continuous-time second-order Δ Σ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.
AB - A continuous-time second-order Δ Σ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.
KW - Voltage controlled oscillator (VCO)
KW - analog-to-digital converter
KW - continuous-time ΔΣ
KW - noise shaping
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U2 - 10.1109/TCSI.2019.2898415
DO - 10.1109/TCSI.2019.2898415
M3 - Article
AN - SCOPUS:85068008080
SN - 1549-8328
VL - 66
SP - 2415
EP - 2425
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 7
M1 - 8648369
ER -