Abstract
The use of pulse-clocked latches has become ubiquitous in commercial unhardened integrated circuits (ICs) both for their performance and power benefits. In this paper, their use in soft-error hardened triple modular redundant (TMR) circuits is presented. The proposed multi-bit, self-correcting, TMR pulse-clocked latch macro provides a low power, high-speed design with high soft-error immunity. The macro includes test modes for delay testing of both individual and TMR copies with minimal area overhead, as well as a non-redundant operating mode. A physical design flow provides spatial separation of redundant logic copies to avoid upsets due to collection in multiple domains. A TMR, 128-bit data, 256-bit key, advanced encryption standard (AES) is fabricated on a 90-nm foundry low-standby power (LSP) process and its hardness verified using error injection simulations and proton beam testing.
Original language | English (US) |
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Article number | 7347448 |
Pages (from-to) | 3040-3048 |
Number of pages | 9 |
Journal | IEEE Transactions on Nuclear Science |
Volume | 62 |
Issue number | 6 |
DOIs | |
State | Published - Dec 2015 |
Keywords
- Advanced encryption standard (AES)
- automated place and route (APR)
- pulse-clocked latches
- radiation hardening by design (RHBD)
- single-event upset (SEU)
- triple modular redundancy (TMR)
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Nuclear Energy and Engineering
- Electrical and Electronic Engineering