High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness

Chandarasekaran Ramamurthy, Srivatsan Chellappa, Vinay Vashishtha, Anudeep Gogulamudi, Lawrence T. Clark

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

The use of pulse-clocked latches has become ubiquitous in commercial unhardened integrated circuits (ICs) both for their performance and power benefits. In this paper, their use in soft-error hardened triple modular redundant (TMR) circuits is presented. The proposed multi-bit, self-correcting, TMR pulse-clocked latch macro provides a low power, high-speed design with high soft-error immunity. The macro includes test modes for delay testing of both individual and TMR copies with minimal area overhead, as well as a non-redundant operating mode. A physical design flow provides spatial separation of redundant logic copies to avoid upsets due to collection in multiple domains. A TMR, 128-bit data, 256-bit key, advanced encryption standard (AES) is fabricated on a 90-nm foundry low-standby power (LSP) process and its hardness verified using error injection simulations and proton beam testing.

Original languageEnglish (US)
JournalIEEE Transactions on Nuclear Science
DOIs
StateAccepted/In press - Dec 4 2015

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Nuclear Energy and Engineering
  • Nuclear and High Energy Physics

Cite this

Ramamurthy, C., Chellappa, S., Vashishtha, V., Gogulamudi, A., & Clark, L. T. (Accepted/In press). High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness. IEEE Transactions on Nuclear Science. https://doi.org/10.1109/TNS.2015.2498919