TY - GEN
T1 - Hardening AES hardware implementations against fault and error inject attacks
AU - Bu, Lake
AU - Kinsy, Michel A.
N1 - Publisher Copyright:
© 2018 Association for Computing Machinery.
PY - 2018/5/30
Y1 - 2018/5/30
N2 - The Advanced Encryption Standard (AES) enables secure transmission of confidential messages. Since its invention, there have been many proposed attacks against the scheme. For example, one can inject errors or faults to acquire the encryption keys. It has been shown that the AES algorithm itself does not provide a protection against these types of attacks. Therefore, additional techniques like error control codes (ECCs) have been proposed to detect active attacks. However, not all the proposed solutions show the adequate efficacy. For instance, linear ECCs have some critical limitations, especially when the injected errors are beyond their fault detection or tolerance capabilities. In this paper, we propose a new method based on a non-linear code to protect all four internal stages of the AES hardware implementation. With this method, the protected AES system is able to (a) detect all multiplicity of errors with a high probability and (b) correct them if the errors follow certain patterns or frequencies. Results shows that the proposed method provides much higher security and reliability to the AES hardware implementation with minimal overhead.
AB - The Advanced Encryption Standard (AES) enables secure transmission of confidential messages. Since its invention, there have been many proposed attacks against the scheme. For example, one can inject errors or faults to acquire the encryption keys. It has been shown that the AES algorithm itself does not provide a protection against these types of attacks. Therefore, additional techniques like error control codes (ECCs) have been proposed to detect active attacks. However, not all the proposed solutions show the adequate efficacy. For instance, linear ECCs have some critical limitations, especially when the injected errors are beyond their fault detection or tolerance capabilities. In this paper, we propose a new method based on a non-linear code to protect all four internal stages of the AES hardware implementation. With this method, the protected AES system is able to (a) detect all multiplicity of errors with a high probability and (b) correct them if the errors follow certain patterns or frequencies. Results shows that the proposed method provides much higher security and reliability to the AES hardware implementation with minimal overhead.
KW - AES
KW - Error correction
KW - Error detection
KW - Non-linearity
KW - Robust codes
UR - http://www.scopus.com/inward/record.url?scp=85049442529&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85049442529&partnerID=8YFLogxK
U2 - 10.1145/3194554.3194649
DO - 10.1145/3194554.3194649
M3 - Conference contribution
AN - SCOPUS:85049442529
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 499
EP - 502
BT - GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PB - Association for Computing Machinery
T2 - 28th Great Lakes Symposium on VLSI, GLSVLSI 2018
Y2 - 23 May 2018 through 25 May 2018
ER -