Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms

TY - JOUR

T1 - Guest Editorial Low-Power, Adaptive Neuromorphic Systems

T2 - Devices, Circuit, Architectures and Algorithms

AU - Basu, Arindam

AU - Chang, Meng Fan

AU - Chicca, Elisabetta

AU - Karnik, Tanay

AU - Li, Hai

AU - Seo, Jae-sun

N1 - Funding Information: Jae-Sun Seo (M’10–SM’17) received the B.S. degree from Seoul National University in 2001, and the M.S. and Ph.D. degrees from the University of Michigan in 2006 and 2010, respectively, all in electrical engineering. He spent graduate research internships at the Intel Circuit Research Laboratory in 2006 and the Sun Microsystems VLSI Research Group in 2008. From 2010 to 2013, he was with the IBM T. J. Watson Research Center, where he was involved in cognitive computing chips under the DARPA SyNAPSE project and energy-efficient integrated circuits for high-performance processors. In 2014, he joined the School of Electrical, Computer and Energy Engineering, ASU, as an Assistant Professor. In 2015, he was a Visiting Faculty at the Intel Circuits Research Laboratory. His research interests include efficient hardware design of machine learning/neuromorphic algorithms and integrated power management. He was a recipient of Samsung Scholarship (2004–2009), the IBM Outstanding Technical Achievement Award (2012), and the NSF CAREER Award (2017). He serves on the Technical Program Committee for ISLPED (2013), ISOCC (2016–2017), DAC (2018), the Review Committee for ISCAS (2017–2018), and on the Organizing Committee for ICCD (2015–2017). Funding Information: Hai (Helen) Li (M’08–SM’16) received the B.S. and M.S. degrees from Tsinghua University, Beijing, China, and the Ph.D. degree from the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA. She currently is a Clare Boothe Luce Associate Professor with the Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA. Prior to that, she was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, Seagate Technology, Bloomington, MN, USA, the Polytechnic Institute of New York University, Brooklyn, NY, USA, and the University of Pittsburgh, Pittsburgh, PA, USA. She has authored or co-authored over 200 technical papers published in peer-reviewed journals and conferences and authored the book Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing (CRC Press, 2011). Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and cross-layer optimization for low power and high performance. She is a Distinguished Member of the ACM. She was the General Chair of ISVLSI, ICCE, ISQED, and GLSVLSI, and the Technical Program Chair of SoCC, iNIS, and GLSVLSI. She received the NSF CAREER Award (2012), the DARPA Young Faculty Award (2013), the TUM-IAS Hans Fisher Fellowship (2017), seven best paper awards, and an additional seven best paper nominations. She serves as Associate Editor for the IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN, the IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, the IEEE TRANSACTIONS OF EMBEDDED COMPUTING SYSTEMS, the IEEE Consumer Electronics Magazine, ACM Transactions on Design Automation of Electronic Systems, and IET Cyber-Physical Systems: Theory & Applications.

PY - 2018/3

Y1 - 2018/3

UR - http://www.scopus.com/inward/record.url?scp=85045100248&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85045100248&partnerID=8YFLogxK

U2 - 10.1109/JETCAS.2018.2810399

DO - 10.1109/JETCAS.2018.2810399

M3 - Editorial

AN - SCOPUS:85045100248

SN - 2156-3357

VL - 8

SP - 1

EP - 5

JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems

JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems

IS - 1

ER -