TY - JOUR
T1 - Go/No-Go testing of VCO modulation RF transceivers through the delayed-RF setup
AU - Acar, Erkan
AU - Ozev, Sule
N1 - Funding Information:
Manuscript received October 31, 2005; revised September 27, 2006. This work was supported by the Semiconductor Research Corporation under Contract 2004-TJ-1247. The authors are with the Electrical and Computer Engineering Department, Duke University, Durham, NC 27708 USA (e-mail: eacar@ieee.org; sule@ee. duke.edu). Digital Object Identifier 10.1109/TVLSI.2007.891082
PY - 2007/1
Y1 - 2007/1
N2 - The increasing share of test and packaging as a percentage of the overall cost for RF transceivers necessitate, radically test new approaches to both wafer-level and final production testing. We present a new system-level test setup for voltage-controlled oscillator (VCO) modulating transceiver architectures that we call the delayed-RF setup, along with a novel, all-digital design-for-testability (DFT) modification that enables coverage of the most important system-level specifications. The delayed-RF setup can be used during wafer sort, thus preventing the packaging of nonfunctional dies. Based on this setup and the DFT technique, we present an automatic test development methodology for FM transceivers using frequency-domain signature analysis. We develop two distinct pass/fail criteria based on eigensignatures and envelope signatures and a test generation algorithm that aims at minimizing the required delay while attaining full coverage of target faults. We develop a fault injection and simulation platform for a VCO-modulation, low-IF transceiver architecture using MATLAB and behavioral models including nonideal response. The proposed methodology enables the automation of the test generation process, thus reduces the test development time. Experimental results have shown a 90% reduction in the required delay thereby reducing the cost of this test hardware item.
AB - The increasing share of test and packaging as a percentage of the overall cost for RF transceivers necessitate, radically test new approaches to both wafer-level and final production testing. We present a new system-level test setup for voltage-controlled oscillator (VCO) modulating transceiver architectures that we call the delayed-RF setup, along with a novel, all-digital design-for-testability (DFT) modification that enables coverage of the most important system-level specifications. The delayed-RF setup can be used during wafer sort, thus preventing the packaging of nonfunctional dies. Based on this setup and the DFT technique, we present an automatic test development methodology for FM transceivers using frequency-domain signature analysis. We develop two distinct pass/fail criteria based on eigensignatures and envelope signatures and a test generation algorithm that aims at minimizing the required delay while attaining full coverage of target faults. We develop a fault injection and simulation platform for a VCO-modulation, low-IF transceiver architecture using MATLAB and behavioral models including nonideal response. The proposed methodology enables the automation of the test generation process, thus reduces the test development time. Experimental results have shown a 90% reduction in the required delay thereby reducing the cost of this test hardware item.
KW - Design-for-testability (DFT)
KW - Frequency-shift keying (FSK)
KW - Loop-back
KW - RF testing
KW - Voltage-controlled oscillator (VCO) modulation architectures
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U2 - 10.1109/TVLSI.2007.891082
DO - 10.1109/TVLSI.2007.891082
M3 - Article
AN - SCOPUS:33847755190
SN - 1063-8210
VL - 15
SP - 37
EP - 46
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
ER -