TY - GEN
T1 - Germanium sulfide-based solid electrolytes for non-volatile memory
AU - Balakrishnan, Muralikrishnan
AU - Kozicki, Michael
AU - Gopalan, Chakravarthy
AU - Mitkova, Maria
PY - 2005
Y1 - 2005
N2 - Next generation memory development is driven by the increasing demand for lower voltage, lower power, and lower cost. It is believed that memories based on charge storage will have difficulty meeting the operational demands of memory when the industry begins manufacturing at geometries beyond the 65 nm node. Many technologies which have been presented as contenders for next generation memory have scalability issues such as the physical size of the device and/or high programming voltage and current, both of which are undesirable for the future memory applications. One potential candidate for future non-volatile solid state memory is the Programmable Metallization Cell (PMC), which is based on a silver- or copper-doped solid electrolyte film sandwiched between a silver or copper anode and an electrochemically inert cathode1. The main benefit of PMC technology is that the information is stored not as charge but as nanoscopic amounts of metal in an electrolyte film which can be placed in the interconnect layers above the silicon circuitry. In our earlier work, we focused on Ag-Ge-Se devices ranging from several μm to 40 nm in dimensions, the key attributes of which are low voltage and current operation, excellent scalability, excellent retention and endurance, and a simple fabrication process2. One consideration for Se-based devices is that they do not tolerate processing temperatures over 200°C since the hosting chalcogenide glass may crystallize in this range and so relatively low temperature back-end-of-line processing (BEOL) is necessary. In the present work, we describe PMC memory devices based on Ag-Ge-S electrolytes. These have excellent temperature stability and are compatible with most BEOL processing in CMOS integrated circuits. Fig.1 shows a schematic cross-section of a basic PMC device structure. The bottom electrode is typically tungsten metal, although it can be any electrochemically inert conductor (e.g., Ni or Al). To make the electrolyte, a 60nm thick Ge-S electrolyte and a 25 nm thick layer of Ag are sequentially deposited in the vias formed in an inter layer dielectric. The Ag is photodissolved into the base glass using a UV source, forming a solid electrolyte with a high Ag ion mobility. The PMC device is completed by capping this structure with a layer of interconnect metal. Fig. 2(a) shows a typical current-voltage behavior of a 240 nm Ag-Ge-S electrolyte device that has been annealed at 300°C for 15 minutes in a N2 ambient and programmed at 10μA. The write threshold voltage is approximately 0.45 V, at which the compliance current of the programming source is reached and the electrodeposition process ceases, leading to the final on resistance. Fig. 2(b) shows the resistance-voltage plot for the same device in which a significant drop in the off resistance from the order of tens of GΩ to an on resistance of 45 kΩ is observed. Note that the on resistance is dependent on programming current; a 1mA current limit leads to an on state in the order of a few hundred Ω. The device returns to its off state at -0.25 V. Fig. 3(a) gives the on state retention plot of a 2.5 μm device annealed at 300°C for 15 minutes in a N2 ambient. The initial high off state of the unwritten device observed in the plot was read at 200 mV. The device was then programmed with 1 V at 10 μA and the on state resistance seen in the plot is approximately 40 kΩ. The on state resistance after 55 hours of testing at a read bias of 200 mV and 20 μA current is closer to 10 kΩ. Fig. 3(b) gives the off state retention plot of the same device after a -2V erase sweep. The off state retention of the device was read at 200 mV and is in the order of tens of GΩ after approximately 13 hours of testing. We will provide further device characteristics and supportive material analysis in the full paper.
AB - Next generation memory development is driven by the increasing demand for lower voltage, lower power, and lower cost. It is believed that memories based on charge storage will have difficulty meeting the operational demands of memory when the industry begins manufacturing at geometries beyond the 65 nm node. Many technologies which have been presented as contenders for next generation memory have scalability issues such as the physical size of the device and/or high programming voltage and current, both of which are undesirable for the future memory applications. One potential candidate for future non-volatile solid state memory is the Programmable Metallization Cell (PMC), which is based on a silver- or copper-doped solid electrolyte film sandwiched between a silver or copper anode and an electrochemically inert cathode1. The main benefit of PMC technology is that the information is stored not as charge but as nanoscopic amounts of metal in an electrolyte film which can be placed in the interconnect layers above the silicon circuitry. In our earlier work, we focused on Ag-Ge-Se devices ranging from several μm to 40 nm in dimensions, the key attributes of which are low voltage and current operation, excellent scalability, excellent retention and endurance, and a simple fabrication process2. One consideration for Se-based devices is that they do not tolerate processing temperatures over 200°C since the hosting chalcogenide glass may crystallize in this range and so relatively low temperature back-end-of-line processing (BEOL) is necessary. In the present work, we describe PMC memory devices based on Ag-Ge-S electrolytes. These have excellent temperature stability and are compatible with most BEOL processing in CMOS integrated circuits. Fig.1 shows a schematic cross-section of a basic PMC device structure. The bottom electrode is typically tungsten metal, although it can be any electrochemically inert conductor (e.g., Ni or Al). To make the electrolyte, a 60nm thick Ge-S electrolyte and a 25 nm thick layer of Ag are sequentially deposited in the vias formed in an inter layer dielectric. The Ag is photodissolved into the base glass using a UV source, forming a solid electrolyte with a high Ag ion mobility. The PMC device is completed by capping this structure with a layer of interconnect metal. Fig. 2(a) shows a typical current-voltage behavior of a 240 nm Ag-Ge-S electrolyte device that has been annealed at 300°C for 15 minutes in a N2 ambient and programmed at 10μA. The write threshold voltage is approximately 0.45 V, at which the compliance current of the programming source is reached and the electrodeposition process ceases, leading to the final on resistance. Fig. 2(b) shows the resistance-voltage plot for the same device in which a significant drop in the off resistance from the order of tens of GΩ to an on resistance of 45 kΩ is observed. Note that the on resistance is dependent on programming current; a 1mA current limit leads to an on state in the order of a few hundred Ω. The device returns to its off state at -0.25 V. Fig. 3(a) gives the on state retention plot of a 2.5 μm device annealed at 300°C for 15 minutes in a N2 ambient. The initial high off state of the unwritten device observed in the plot was read at 200 mV. The device was then programmed with 1 V at 10 μA and the on state resistance seen in the plot is approximately 40 kΩ. The on state resistance after 55 hours of testing at a read bias of 200 mV and 20 μA current is closer to 10 kΩ. Fig. 3(b) gives the off state retention plot of the same device after a -2V erase sweep. The off state retention of the device was read at 200 mV and is in the order of tens of GΩ after approximately 13 hours of testing. We will provide further device characteristics and supportive material analysis in the full paper.
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U2 - 10.1109/DRC.2005.1553049
DO - 10.1109/DRC.2005.1553049
M3 - Conference contribution
AN - SCOPUS:33751337521
SN - 0780390407
SN - 9780780390409
T3 - Device Research Conference - Conference Digest, DRC
SP - 47
EP - 48
BT - 63rd Device Research Conference Digest, DRC'05
T2 - 63rd Device Research Conference, DRC'05
Y2 - 20 June 2005 through 22 June 2005
ER -