This paper discusses an extension to an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules. This PDK is designed for 45nm feature sizes and is utilized for use in VLSI research, computer architecture, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell library, MIPS® processor and associated GNU-compliant compiler and the necessary support files to enable full chip place and route and verification for System on Chip designs. An analog and digital system test chip is also included with this PDK-extension allowing exploration of nanometer-based VLSI designs.