TY - GEN
T1 - Ferroelectric FET analog synapse for acceleration of deep neural network training
AU - Jerry, Matthew
AU - Chen, Pai Yu
AU - Zhang, Jianchi
AU - Sharma, Pankaj
AU - Ni, Kai
AU - Yu, Shimeng
AU - Datta, Suman
N1 - Funding Information:
In conclusion, we experimentally demonstrate a FeFET analog synapse based on partial polarization switching, for acceleration of on-chip learning in deep neural networks. A transient Presiach model quantitatively captures the dynamics of voltage controlled partial polarization switching in 10nm HZO films. The fabricated FeFET synapse exhibits symmetric 5-bit potentiation and depression characteristics, resulting in 90% accuracy for image recognition after training on the MNIST database. Further, the 75ns experimental programing pulse width improves training time on 1M images by 1000× compared to demonstrated RRAM devices while maintaining a 10× area advantage over SRAM. VI. ACKNLOWLEDGEMENTS This project was supported by the National Science Foundation under grant 1640081 and 1552687, and the Nanoelectronics Research Corporation (NERC), a wholly-owned subsidiary of the Semiconductor Research Corporation (SRC), through Extremely Energy Efficient Collective Electronics (EXCEL), an SRC-NRI Nanoelectronics Research Initiative under Research Task IDs 2698.001. The authors thank useful discussion with Wilfried Haensch of IBM Research, Yorktown Heights.
Publisher Copyright:
© 2017 IEEE.
PY - 2018/1/23
Y1 - 2018/1/23
N2 - The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar/pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark onchip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.
AB - The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar/pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark onchip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.
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U2 - 10.1109/IEDM.2017.8268338
DO - 10.1109/IEDM.2017.8268338
M3 - Conference contribution
AN - SCOPUS:85045181722
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 6.2.1-6.2.4
BT - 2017 IEEE International Electron Devices Meeting, IEDM 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 63rd IEEE International Electron Devices Meeting, IEDM 2017
Y2 - 2 December 2017 through 6 December 2017
ER -