Ferroelectric FET analog synapse for acceleration of deep neural network training

Matthew Jerry, Pai Yu Chen, Jianchi Zhang, Pankaj Sharma, Kai Ni, Shimeng Yu, Suman Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Scopus citations

Abstract

The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar/pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark onchip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.

Original languageEnglish (US)
Title of host publication2017 IEEE International Electron Devices Meeting, IEDM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages6.2.1-6.2.4
ISBN (Electronic)9781538635599
DOIs
StatePublished - Jan 23 2018
Event63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
Duration: Dec 2 2017Dec 6 2017

Other

Other63rd IEEE International Electron Devices Meeting, IEDM 2017
CountryUnited States
CitySan Francisco
Period12/2/1712/6/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Jerry, M., Chen, P. Y., Zhang, J., Sharma, P., Ni, K., Yu, S., & Datta, S. (2018). Ferroelectric FET analog synapse for acceleration of deep neural network training. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 6.2.1-6.2.4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268338