Abstract
The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar/pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark onchip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.
Original language | English (US) |
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Title of host publication | 2017 IEEE International Electron Devices Meeting, IEDM 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 6.2.1-6.2.4 |
ISBN (Electronic) | 9781538635599 |
DOIs | |
State | Published - Jan 23 2018 |
Event | 63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: Dec 2 2017 → Dec 6 2017 |
Other
Other | 63rd IEEE International Electron Devices Meeting, IEDM 2017 |
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Country | United States |
City | San Francisco |
Period | 12/2/17 → 12/6/17 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry