Exploring sub-20nm FinFET design with predictive technology models

Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

208 Scopus citations

Abstract

Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.

Original languageEnglish (US)
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Pages283-288
Number of pages6
DOIs
StatePublished - Jul 11 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other49th Annual Design Automation Conference, DAC '12
CountryUnited States
CitySan Francisco, CA
Period6/3/126/7/12

Keywords

  • FinFET
  • SPICE
  • multi-gate
  • predictive models
  • scaling theory

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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  • Cite this

    Sinha, S., Yeric, G., Chandra, V., Cline, B., & Cao, Y. (2012). Exploring sub-20nm FinFET design with predictive technology models. In Proceedings of the 49th Annual Design Automation Conference, DAC '12 (pp. 283-288). (Proceedings - Design Automation Conference). https://doi.org/10.1145/2228360.2228414