@inproceedings{8dc7f6fca44c46c8ac3f2540347d85ee,
title = "Exploring sub-20nm FinFET design with predictive technology models",
abstract = "Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.",
keywords = "FinFET, SPICE, multi-gate, predictive models, scaling theory",
author = "Saurabh Sinha and Greg Yeric and Vikas Chandra and Brian Cline and Yu Cao",
year = "2012",
doi = "10.1145/2228360.2228414",
language = "English (US)",
isbn = "9781450311991",
series = "Proceedings - Design Automation Conference",
pages = "283--288",
booktitle = "Proceedings of the 49th Annual Design Automation Conference, DAC '12",
note = "49th Annual Design Automation Conference, DAC '12 ; Conference date: 03-06-2012 Through 07-06-2012",
}