Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA)

Aviral Shrivastava, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Energy consumption is emerging as a critical design concern for programmable embedded systems. Many Reduced Bit-width Instruction Set Architectures (rISA) (e.g., ARM Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in non-cached rISA architectures as a byproduct of code size reduction. In this paper we present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and non-cached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages475-477
Number of pages3
StatePublished - 2004
Externally publishedYes
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: Jan 27 2004Jan 30 2004

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period1/27/041/30/04

Fingerprint

Data storage equipment
Energy conservation
Energy utilization
Information use
Embedded systems
Byproducts
Electric power utilization
Code generation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shrivastava, A., & Dutt, N. (2004). Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA). In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 475-477)

Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA). / Shrivastava, Aviral; Dutt, Nikil.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 475-477.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shrivastava, A & Dutt, N 2004, Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA). in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 475-477, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan, 1/27/04.
Shrivastava A, Dutt N. Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA). In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 475-477
Shrivastava, Aviral ; Dutt, Nikil. / Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA). Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. pp. 475-477
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