Energy-aware error control coding for flash memories

Veera Papirla, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations


The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an algorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive '01' and '10' bit-patterns during error control coding. We show that the algorithm does not change the error correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33% of write energy and 31% of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%.

Original languageEnglish (US)
Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9781605584973
StatePublished - 2009
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: Jul 26 2009Jul 31 2009

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Country/TerritoryUnited States
CitySan Francisco, CA


  • Endurance
  • Error control coding
  • Flash memories
  • Low-power design

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


Dive into the research topics of 'Energy-aware error control coding for flash memories'. Together they form a unique fingerprint.

Cite this